Help Wanted? Help Given! 3D-IC design is ready for take-off

By Steve Smith |  1 Comment  |  Posted: August 12, 2013
Topics/Categories: EDA - IC Implementation  |  Tags: , , ,  | Organizations: , ,

Steve Smith of SynopsysSteve Smith is senior director of 3D-IC marketing at Synopsys.

The 5th Design for 3D (D43D) workshop took place in Grenoble, France back in June, hosted by LETI at the MINATEC premises. Having participated and/or presented for the last three editions, this event provided an opportunity for me to explain the status of Synopsys’ 3D-IC effort, and of my own.

I started dealing with 3D-IC integration back in 2010. At that time, everything was still being devised, and nothing was carved in stone, but the general sentiment was that the lack of design tools and methodologies presented the major roadblock. Our partners and customers wanted our help.

We/I first tried to understand something: more than 2D-IC integration had been around for quite a while in the form of system-in-package (SiP) and package-over-package (PoP): figure 1 shows a then very advanced example of a combination of SiP and PoP: the cross section shows two packages, the bottom one with an application processor, the top one with two memory die, stacked one on top of another.

A combination of SIP and POP approaches to more than 2D-IC integration (Source: TechInsights 2010)

Figure 1 A combination of SIP and POP approaches to more than 2D-IC integration (Source: TechInsights 2010)

Even through-silicon-via (TSV) had been around for quite a while – the first US patent, # 3,044,909, was filed by William Shockley in 1958, even before the ’Traitorous Eight’ gave birth to the IC at Fairchild. May I say it was a solution without a problem for more than half of a century?

William Shockley’s a958 patent for TSVs (Source: Google Patents)

Figure 2 William Shockley’s a958 patent for TSVs (Source: Google Patents)

What was different now, and how could we help? Understanding technology trends and their timeline is critical to driving the EDA roadmap, as blind investments too often lead to dead ends. We were fortunate that we had the opportunity to collaborate with our leading semiconductor IDM, fabless, and foundry partners.

With their help, we identified the main categories of ‘more than 2D-IC’ emerging, and agreed with them to focus our resources on silicon interposers, the so-called 2.5D-IC. This was an intermediate step in the ladder towards 3D-IC integration, having most of the 3D-IC advantages without its drawbacks.

Existing design tools, methodologies, and flows could be upgraded to deal with 2.5D-IC integration, as most of the 2.5D-IC design flow is identical to an advanced 2D design flow, and a limited number of new capabilities and features was necessary to make existing 2D EDA technology 2.5D-aware and capable. These include support of IEEE standards for 3D-IC test, a new 45° RDL router in P&R, support of 3D structures such as TSV, micro-bumps, etc in RC extraction, multi-technology support in SPICE simulation, STA, and DRC.

Xilinx is the best proof of the revolutionary results enabled by an evolutionary approach: in 2011, they introduced the world’s first example of homogeneous integration of logic onto a silicon interposer, the largest FPGA ever built: 7 billion transistors onto an approximately 800 square millimetre silicon interposer. Then in 2012 they introduced the world’s first heterogeneous integration of logic onto a silicon interposer, which added high-speed SerDes I/O to the high-performance FPGA, further increasing the breadth of applications that can leverage Virtex7. At D43D, Xilinx’ Brendan Farley suggested that the next step would be adding memory stacks, which would enable up to 2Tbit/s of bandwidth between the logic and the memory, as a “simple extension of existing work.” This is only the beginning!

I am proud to say that the help our partners and customers wanted has been given. An evolutionary transition from 2D- to 3D-IC integration has been devised, and successfully demonstrated; Synopsys implementation, simulation, and verification tools have been enhanced to address 2.5D-IC designs; the eco-system is in place, and multiple, foundry-certified design flows are now available. Synopsys has recently been recognized as one of only two EDA vendors that can provide the full flow.

Design and EDA are no longer a roadblock. One ingredient has proven critically important: collaboration. We have benefited from the willingness of our partners and customers to work with us, incrementally developing, debugging, and enhancing the manufacturing technology, the design tools, and the methodologies and flows. They have accepted temporary work-arounds, acknowledging that technology is only seldom perfect at its inception, and knowing that joint efforts would pay off.

The recent introduction of non-planar CMOS transistors at 20nm, and the significant progress of standard DDR memories may have delayed the take-off, but 3D-IC is definitely a good idea, and good ideas have a tendency to come back. We may be ‘taxiing’ for a little longer, but we’re ready for take-off as soon as we’re cleared.

I am optimistic by nature, and I do look forward to the 6th D43D workshop, which will take place in Lausanne, Switzerland in June 2014. I am confident that the inevitable transition from 2D- to 3D-IC integration will progress, as many applications, regardless of the manufacturing process technology node can benefit from this new way of fulfilling Moore’s law.


Steve Smith is currently responsible for Synopsys’ 3D-IC strategy and marketing. He has been with Synopsys for 15 years, having served in various functional verification and design implementation marketing roles. He has worked in the electronic design automation and computer industries for more than 30 years in a variety of senior positions including marketing, applications engineering and software development. Prior to Synopsys, Steve worked at Viewlogic, CrossCheck, Teradyne, Unisys and ICL. Steve holds a bachelor’s degree in statistics and numerical analysis from Lancaster University, England.


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