Antun Domic of Synopsys tackles the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Characterizing standard-cell defect mechanisms helps improve IC testing
There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.
A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy. Here's what’s new in the proof-of-concept simulator, and how you can participate to refine the Accellera Systems Initiative’s work for standardization.
View All Sponsors