Think like designers to fill the SoC verification gap
Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
dataflow
Decoupled constraint modelling – a design methodology for hard real-time systems on chip
Using UML to define a software-defined modem SoC in terms of decoupled constraints - the order of activities, the timing they have to meet, and the available resources