UVM register layer

October 11, 2013
Axel Scherer is a solutions architect at Cadence Design Systems in Massachusetts, leading the Incisive Product Expert Team for testbenches in general and the Universal Verification Methodology (UVM) in particular.

Learn the tricks of the UVM Register Layer

Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:

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