Expert Insights - EDA

John Ferguson  |  April 28, 2014

Protecting IP in a collaborative signoff environment

The encryption chain for today's highly collaborative designs needs to be managed with care.
Pranav Ashar  |  April 16, 2014

Reset optimization pays big dividends before simulation

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Joe Kwan  |  April 3, 2014

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
Chris Tice  |  March 17, 2014

The rise of hardware-assisted verification

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  
Warren Stapleton  |  February 27, 2014

Next wave of innovation in verification technology must come from integration

The next boost to verification productivity will come from the integration of multiple strategies and tools.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Lisa Piper  |  February 26, 2014

Complexity drives smart reporting

Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.
Mark Bollar  |  February 11, 2014

The new landscape of advanced design

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.
Sudhakar Jilla  |  February 6, 2014

Concurrency tackles MCMM issues head-on

The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
Topics: EDA - IC Implementation, Verification  |  Tags: ,   |  Organizations:   |  
Mark Bollar  |  January 28, 2014

Are advanced designs only possible at emerging process nodes?

Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.
Jean-Marie Brunet  |  January 20, 2014

Patterning choices loom for 10nm and beyond

It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?

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