Expert Insights - EDA

David Fried  |  December 3, 2013

Lithography challenges threaten the cost benefits of IC scaling

The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
Topics: EDA - DFM  |  Tags: , , , , , , , , ,   |  Organizations:   |  
Brian Fuller  |  November 11, 2013

Goodbye to the mixed-signal black box

In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,   |  
Jack Erickson  |  November 1, 2013

Slow winter or new spring for hardware design?

Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Topics: EDA - ESL  |  Tags: , , ,   |  Organizations:   |  
Piyush Sancheti  |  October 16, 2013

The requirements for complete RTL signoff

Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Topics: EDA - IC Implementation, Verification  |  Tags: ,   |  Organizations:   |  
Axel Scherer  |  October 11, 2013

Learn the tricks of the UVM Register Layer

Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  
Adnan Hamid  |  October 7, 2013

Think like designers to fill the SoC verification gap

Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:   |  
Steve Smith  |  August 12, 2013

Help Wanted? Help Given! 3D-IC design is ready for take-off

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,   |  
Dan Benua  |  July 25, 2013

Formal techniques tackle the SoC verification challenge

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
Graham Bell  |  July 3, 2013

The challenge of clock domain crossings – and some solutions

Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
Graham Bell  |  May 14, 2013

Building an RTL sign-off flow

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.

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