Expert Insights - EDA

Steffen Schulze  |  January 13, 2014

Consider your options for future nodes

If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.
Neil Songcuan  |  January 7, 2014

Using HAPS to streamline IP to SoC integration

The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Topics: IP - Assembly & Integration, EDA - IC Implementation  |  Tags: , ,   |  Organizations:   |  
Mick Posner  |  December 16, 2013

Consistency key to gaining the advantages of IP integration

Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
Carey Robertson  |  December 9, 2013

FinFET parasitics come under control

Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
Topics: EDA - DFM, IC Implementation  |  Tags: , , , ,   |  Organizations:   |  
David Fried  |  December 3, 2013

Lithography challenges threaten the cost benefits of IC scaling

The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
Topics: EDA - DFM  |  Tags: , , , , , , , , ,   |  Organizations:   |  
Brian Fuller  |  November 11, 2013

Goodbye to the mixed-signal black box

In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,   |  
Jack Erickson  |  November 1, 2013

Slow winter or new spring for hardware design?

Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Topics: EDA - ESL  |  Tags: , , ,   |  Organizations:   |  
Piyush Sancheti  |  October 16, 2013

The requirements for complete RTL signoff

Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Topics: EDA - IC Implementation, Verification  |  Tags: ,   |  Organizations:   |  
Axel Scherer  |  October 11, 2013

Learn the tricks of the UVM Register Layer

Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  
Adnan Hamid  |  October 7, 2013

Think like designers to fill the SoC verification gap

Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:   |  

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