Anders Nordstrom |  January 5, 2016
Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.
Walden Rhines |  January 4, 2016
Dr Walden Rhines, chairman and CEO of Mentor Graphics, opens a two-part analysis by looking back at the dominant design and business trends in 2015.
Steve Pateras |  December 29, 2015
Behind the drivers for memory BIST innovation in areas such as power-on self-test, destructive and non-destructive techniques, and faster memory repair.
Bruce McGaughy |  October 28, 2015
Although FastSPICE simulators are in almost every design flow, requirements are moving beyond the capabilities they can provide. Parallel processing provides a solution.
Nasib Naser |  October 19, 2015
Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
Amol Herlekar |  October 8, 2015
A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
Lauro Rizzatti |  September 12, 2015
In-circuit emulation is attractive but brings with it debug-visibility issues. There are ways to restructure the environment to make bug hunting much more deterministic.
Warren Kurisu |  August 24, 2015
The wearables market is booming. Successful development depends on assembling the right software and hardware tools. Here's a primer on what to look for.
Jai Durgam |  August 19, 2015
A look at some of the quality and safety requirements that must be met when developing and applying semiconductor IP to the automotive sector.
Mick Posner |  August 4, 2015
The introduction of bigger FPGAs enables more complex prototypes - but makes debugging more of a challenge. Here's one way to address the issue.