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April 29, 2021

DVCon Europe best paper assesses clock design

The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:
March 2, 2021
streaming scan network featured image

Streaming Scan Network technology delivers ‘no compromise’ DFT for AI designs

A new technique is especially efficient for AI chips with modular, tiled design strategies leveraging multiple instantiations of the same cores.
July 28, 2020
Jay Jahangiri, Product Manager for Mentor, a Siemens Business

Catch the next wave in DFT automation

It is easier than ever to build a flexible, resilient, and end-to-end hierarchical DFT flow with smart automation.
Expert Insight  |  Topics: EDA - DFT  |  Tags:   |  Organizations: ,
May 26, 2020
cloud computing efficiencies with calibre for physical verification

How cloud computing is now delivering efficiencies for IC design

A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
April 24, 2020
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

How to gain a competitive edge with advanced DFT

Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
November 7, 2019
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

International Test Conference celebrates 50 years of advancing test technology

It's the fiftieth International Test Conference this year. How much has been achieved and how much more work is there to do to ensure that we can keep building chips that do what they are supposed to?
Expert Insight  |  Topics: EDA - DFT  |  Tags:   |  Organizations: , , ,
September 9, 2019

Getting better results faster with a unified RTL-to-GDSII product

Complex SoCs need systemic optimisation to achieve best time to results, enabled by the use of a unified RTL-to-GDSII flow underpinned by a unified data model.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
August 15, 2019
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

Achieving more efficient hierarchical DFT for Arm subsystems

Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Expert Insight  |  Topics: EDA - DFT, - EDA Topics  |  Tags: ,   |  Organizations: ,
August 9, 2019
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Spreading the word on formal in Bangalore

Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
April 2, 2019

High-level synthesis for AI: Part Two

How Chips&Media used HLS on the development of a computer vision IP block.

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