It is easier than ever to build a flexible, resilient, and end-to-end hierarchical DFT flow with smart automation.
A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
It's the fiftieth International Test Conference this year. How much has been achieved and how much more work is there to do to ensure that we can keep building chips that do what they are supposed to?
Complex SoCs need systemic optimisation to achieve best time to results, enabled by the use of a unified RTL-to-GDSII flow underpinned by a unified data model.
Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
How Chips&Media used HLS on the development of a computer vision IP block.
The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.
Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
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