Chipmaker

October 28, 2014
Featured image for hybrid testbench article

Harness virtual machines to create an efficient ‘live’ hybrid testbench

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
October 18, 2014
Soft-blocked floorplan

Placement optimizations push power and clock on Cortex-M7 project

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
October 6, 2014
Power grid signal track blocking

ARM, TSMC design explores 16nm finFET issues

ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,   |  Organizations: ,
September 2, 2014
Intel's trigate is among the structures to be modeled by the revised BSIM4

Design enablement and entitlement for 14/16nm finFET processes

How EDA tools are evolving to make it possible to design with finFET processes.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations: , ,
August 27, 2014
Prasad Saggurti is the product marketing manager for embedded memory IP at Synopsys.

Six key criteria for deciding to migrate to a finFET process

Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Expert Insight  |  Topics: EDA - IC Implementation, IP - Selection  |  Tags: , ,   |  Organizations: , , , , ,
July 25, 2014
Steven Cline is a senior design automation Manager at Altera’s Austin Technology Center, focusing on design-flow automation for traditionally placed and routed blocks and custom FPGA IP used on Altera’s advanced FPGA products.

Using standardized design flows to cut time to tape-out – and speed design-flow evolution

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Expert Insight  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , , ,   |  Organizations: , ,
June 15, 2014
Chips on a wafer

Early tape-out: smart verification or expensive mistake?

Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?
June 10, 2014
High-speed I/O eye diagram - thumbnail

Zeroing in on the problems of fast board-level interconnect

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
April 22, 2014

Accelerating multi-corner multi-mode sign-off using the Lynx Design System

Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.
Article  |  Topics: IP - Design Management, EDA - Verification  |  Tags: , , , ,   |  Organizations:
March 24, 2014
HAPS-DX

Prototyping solutions for validation of complex ASIC IP

An in-depth look at the role of FPGA-based prototyping and the validation use cases it offers when integrating complex blocks.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , ,   |  Organizations: ,

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