Sigasi creates SDK for custom editors
Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.
Verilog
How to optimize your testbench-to-DUT connections
Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.
Real Intent updates linter for aviation, Mathworks and SystemVerilog
Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
Real Intent puts the accent on debug with new Ascent IIV release
More than 20 new features and improvements are added to the static functional tool.