Synopsys speeds ATPG, adds ISO 26262 certification
Synopsys has introduced TetraMAX II, a faster and more parallelisable ATPG and diagnostics solution, which is now also certified for use in ISO 26262 compliant automotive designs.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
EEMBC looks into heterogeneous compute
EEMBC has turned its attention to heterogeneous computing with plans to create a new set of benchmarks.
Mentor’s PADS family extended for AMS, DDR and electrical DRC
Mentor Graphics has added four new units to its PADS PCB family addressing increasing complexity in mainstream design.
DTCO points to sub-10nm optimizations
DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
What’s the shortest time in the universe?
“It’s the time between putting out an open-source ARM core and getting a letter from an ARM lawyer,” says UC Berkeley professor Krste Asanovic. So, some design teams are turning to IP that started out as open source to provide more scope for experimentation.
RC extraction from ‘virtual fab’ models may speed PDK availability
Electrical analysis facility does RC extraction on virtual fab models, accelerating the availability of early PDKs for new processes
DFT to expand its role for long-term yield
Design for test could look quite different in five years’ time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
2D tools adapt to create smaller monolithic 3DIC designs
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
Minimize memory moves for greener data centers
Deep pipelines and dynamic memory sharing may provide the key to the development of faster and more efficient server-farm blades as the focus in hardware design moves to augmenting conventional processors with specialized accelerators.
ARM accelerates POP deployment for Cortex-A73
A faster implementation program for the POP support IP for ARM’s cores has delivered a 16nm finFET package for the Cortex-A73 shortly after the core’s Computex launch.