How to optimize your testbench-to-DUT connections
Testbench connections often depend on the virtual interface feature of SystemVerilog but other options – like abstract classes – can help.
Testbench connections often depend on the virtual interface feature of SystemVerilog but other options – like abstract classes – can help.
In the first of a weekly series on China’s evolving design sector, we look at how the Mentor President and CEO identifies some of the key drivers.
Researchers working at Dongguk University have found thinning layers of copper iodide can make transparent, high-mobility p-channel transistors
IEDM plans to expand its range of coverage for the 2019 event to encompass a range of novel computing platforms, from neuromorphic architectures to machines that emulate thermodynamic systems.
DVCon USA is coming soon. Mentor’s 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
A new paper describes a case study for a pressure-sensing IoT application based on the ARM DesignStart platform and Mentor IoT tool flow.
Automotive AI specialist FABU has licensed a portfolio of IP from Synopsys to help assemble ISO 26262-compliant SoCs
Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
It’s been a long time coming, but silicon photonics is now entering commercial design for networking and grabbing attention in autonomous driving and sensors.
A report put together by Europe’s HiPEAC high-performance computing research network argues computing is at an architectural turning point