Accellera sets up group for one-stop verification stimulus
Accellera has set up a working group to develop a language-independent way of capturing and managing test stimuli that can be used across a wide range of verification environments.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Mentor extends industrial embedded offering
New portfolio integrates and extends existing industrial embedded tools to meet the demands of Industry 4.0
Speeding up simulation using native System Verilog transactors
Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
ARM to upgrade smartphone processing with Cortex-A72 combination
ARM has launched a 64bit processor core aimed at high-end mobile phones, coupled to a new graphics processor and cache-coherent interconnect.
Cadence updates Sigrity tools and license options
Cadence Design Systems has added LPDDR4 support and a topology explorer to its Sigrity lineup for signal and power integrity analysis of PCB-based designs, as well as more flexible licensing options.
ARM to provide safety docs for real-time processors
ARM has picked up TÜV Süd certification for a version of its C compiler and produced an ISO 26262 documentation pack for the Cortex-R5 processor
Ambiq uses subthreshold techniques to cut power on ARM MCUs
Research by the University of Michigan into subthreshold circuit design has led to spinoff company Ambiq Micro creating a family of microcontrollers that it claims provide an ARM Cortex-M4F with power consumption at levels normally associated with an M0+.
Cadence updates Xtensa with memory and power saving features
Cadence Design Systems has launched the 11th generation of Tensilica Xtensa customizable processors, with changes for VLIW, power-saving caches and memory accesses.
CEA-Leti deals with heat issue on monolithic 3DIC
At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.
Cadence high-level synthesis changes deal with congestion
SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.