ARM to upgrade smartphone processing with Cortex-A72 combination

By Chris Edwards |  No Comments  |  Posted: February 3, 2015
Topics/Categories: Blog - Embedded, IP  |  Tags: , , ,  | Organizations:

ARM has launched a 64bit processor core aimed at high-end mobile phones, coupled to a new graphics processor and cache-coherent interconnect. The company claims the combination provides 50 times more aggregate compute power than top-end designs from five years ago.

Designed primarily for the 16nm finFET processes such as TSMC’s 16FF+, the Cortex-A72, formerly codenamed Maya, has ten licensees so far and is designed to work with the Mali-T880 and CoreLink CCI-500 interconnect, as well as the A53 as the “little CPU” in a typical Big.Little configuration.

“They have been designed and optimised together,” said Ian Ferguson, vice president of segment marketing at ARM. Although he acknowledged analysts’ concerns about the market for smartphones stagnating, “we see more interest from people in using the phone as their primary compute platform. We see people creating content on these devices rather than just consuming them. We see over the coming years interesting ways to interact with these devices”.

Augmented reality

Ferguson said the company expects more focus on image processing using the phone’s camera to recognise people and gestures, citing one potential application a golf-swing adviser.

“We think the A72 will drive the premium phone experience in 2017,” Ferguson claimed.

Running at up to 2.5GHz on 16FF+, for which ARM is providing a POP IP design kit, the company claims the core compute performance of the A72 is approximately 3.5 times the performance of existing A15-based designs based on 28nm processes. This is, according to ARM, with a three-quarter reduction in energy consumption at equivalent performance. “We’ve done things in the micro architecture to improve the energy efficiency,” Ferguson said, pointing to techniques to reduce off-chip memory accesses. He added: “Some of the performance improvement comes from process nodes.”

Ferguson said ARM is not releasing technical details of the pipeline and micro architecture until later this year, probably the April timeframe.

For applications involving augmented reality and similar image-processing focused applications, Ferguson said he expected those phone designs to use additional specialist processors, such as those provided by Movidius.

“What we are saying here is that what is shifting is that we are putting enough capability into the handset to do this processing locally, instead of pushing up into the cloud,” Ferguson said.

The local processing would help with healthcare applications and the legal position, particularly in the US, surrounding the confidentiality of data, Ferguson added. “People are starting to do things such as detect heart irregularities by plugging microphones into their phones.”

Cadence Design Systems was among the first to launch EDA tool and IP support for the A72 and its associated cores. The company is providing a reference flow for the cores on 16FF+, supporting both the Artisan libraries and the POP kit.

“We collaborated closely with ARM to co-optimize our advanced digital implementation and signoff solutions, system-to-silicon verification tools and IPs with the ARM Cortex-A72 processor, and we’re already seeing excellent results with early high-end mobile customers,” said Chi-Ping Hsu, senior vice president and chief strategy officer for EDA at Cadence.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors