Mentor Graphics

October 2, 2013
tdf-ment-lde-featim

Catching layout-dependent effects on-the-fly

New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , ,   |  Organizations:
July 31, 2013
Featured image of ASIC chip plot - Dot Hill case study

RAID vendor Dot Hill adopts OVM flow for reliability

How the company migrated to an OVM-based methodology to design and verify a 30 million-gate ASIC design, on the path to UVM.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , ,   |  Organizations: ,
May 8, 2013
Segement from PCB design rule schematic

Keeping high-speed designs clean with ERC

Electrical rule checks (ERC) are now available to deal with increasing PCB design complexity, speed project delivery and protect the intellectual property within them.
April 30, 2013
tdf-ment-socint-featimg

Knock down the wall to SoC integration

SoC integration can be accelerated by using virtualization to make the benefits of emulation more accessible to both hardware and software engineers.
Article  |  Topics: Embedded Topics, Embedded - Integration & Debug  |  Tags: , , ,   |  Organizations:
April 24, 2013
Colin Walls

The rush to open source tools

Mind how you go. The only truly free thing about open source tools is the download itself. There is, however, a 'third way', matching professional support to these often useful options.
Expert Insight  |  Topics: Embedded - Architecture & Design, Integration & Debug, User Experience  |  Tags: , ,   |  Organizations: ,
April 1, 2013
tdf-ment-waivers-fig1-featim

Improving SoC productivity through automatic design rule waiver processing for legacy IP

You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
Article  |  Topics: IP - Assembly & Integration, EDA - DFM, Verification  |  Tags: , , ,   |  Organizations: ,
January 18, 2013
tdf-jan13-ment-esl-featim

Get more out of system architectures

This case study shows how the evaluation of various design options requires a thorough approach to system-level modeling.
Article  |  Topics: EDA - ESL  |  Tags: ,   |  Organizations:
December 3, 2012

Overcoming dummy fill deck limitations for analog design

CSR used a customized approach to automated dummy fill layout for AMS to address layer density and device matching issues in standard flows aimed at digital SoCs.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , ,   |  Organizations: ,
November 27, 2012
LTTng logo

How LTTng enables complex multicore system development

The Linux Trace Tookit next generation provides open source tracer technology that helps surmount debug and optimization challenges
Article  |  Topics: Embedded - Integration & Debug  |  Tags: , , ,   |  Organizations: ,
November 16, 2012
Stephen Pateras

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - DFT  |  Tags: , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors