EDA

Parasitic extraction has to take more account of inductive effects as operating frequencies rise and feature sizes shrink in complex SoCs.

A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.

SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.

A look at the device types defined by the Compute Express Link (CXL) standard.

A look at the key protocols that control the Compute Express Link (CXL) standard for connecting CPUs and accelerators in hetereogenous computing environments.

A guide to the emerging Compute Express Link (CXL) standard, which links CPUs and accelerators in heterogenous computing environments.

The Portable Stimulus Standard helps overcome many of the verification challenges inherent in the strict requirements of ISO 26262.

Complex SoCs need systemic optimisation to achieve best time to results, enabled by the use of a unified RTL-to-GDSII flow underpinned by a unified data model.

Using a hardware root of trust and a secure development lifecycle process to form the basis of a better approach to developing and implementing more secure complex SoCs.

Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.