EDA

SoC suppliers building the key components for hyperscale data centres need access to the latest IP to handle functions such as PCIe, DDR5, cache coherency, NVMe SSDs, and the highest-bandwidth Ethernet implementations.

Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.

Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.

The doctor was 'in' during last month's DVCon and here highlights some of the main issues in formal raised by delegates at the verification conference.

This defect and fault injection primer looks at how to standardize definitions, decide injection volume, measure activity, manage simulation, optimize test time and more.

How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.

UPF provides a useful way to describe the power-management strategies that should be applied to a design, but using it introduces a number of challenges during low-power debugging.

The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.

An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.

In a continuous-build design flow, at which level should your error markers be addressed?