EDA

Knowledge, intelligence and optimization are key to managing the logistical disruption seen since the Covid-19 outbreak.

Fast emerging options, like RISC-V, could foster massive growth in design but verification still needs commercial tools, a Semicon West panel found.

3D-IC presents major connectivity challenges in maintaining a golden netlist and managing necessary exceptions. Learn how to manage them.

Symmetry verification for analog and custom IC needs to evolve beyond current time-consuming and hard-to-use techniques.

NVMe over Fabrics (NVMe-oF) extends the memory standard for burgeoning data traffic and the demands of AI and machine learning.

How to work with the Compute Express Link and protocols such as MESI to maintain cache coherency.

CDC-related metastability is hard to catch by hand and processes are error prone. Tools offer a more comprehensive approach.

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.

What are the options and how do you balance overarching CAD requirements and personal preferences?

Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.