Fly the friendly skies with automated CDC verification for DO-254
CDC-related metastability is hard to catch by hand and processes are error prone. Tools offer a more comprehensive approach.
EDA
A quick and easy way to calculate P2P resistance and current density
Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
Layout customization improves productivity in design and verification flows
What are the options and how do you balance overarching CAD requirements and personal preferences?
Toward usable and scalable DFT for 3D IC design
Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.
Executable specifications boost SoC and IP efficiency
Automating executable specifications as they evolve can deliver major efficiencies.
Use digitalization to mitigate the automotive MCU shortage
The Covid-driven MCU shortage for ECUs and elsewhere in vehicle design can bring entire production lines to a halt if not properly managed.
Why comprehensive memory layout verification needs automated reliability checks
Because of the high analog content in memory designs, designers must understand how various effects impact reliability and performance.
Manage today’s advanced vehicle networks E/E design challenges
Linking multiple disciplines, and fully accounting for networks and distributed functionality are vital to automotive E/E design.
Assure diagnostic coverage from RTL to gate level during analysis for functional safety
Generating accurate ASIL metrics early in the functional safety lifecycle, reduces time-to-certification for ISO26262.
Siemens’ Sawicki puts priority on scaling in processes, productivity and systems
More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
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