EDA

How Mentor develops and works with partners to prepare each version of its Calibre DFM platform to be ready for the introduction of each new process node.

Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.

Part two of this feature describes three use-cases that exploit the VirtuaLAB technology in HDMI, PCIe and Ethernet designs.

This two-part article describes advantages when using a hardware emulation platform in virtual mode compared with in-circuit-emulation.

Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.

CAA is a valuable tool available to both design engineers and foundries to help them avoid layout-dependent effects during manufacturing.

This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.

How Chips&Media used HLS on the development of a computer vision IP block.

The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.

Automated voltage-aware DRC addresses the reliability verification challenges in today’s high-voltage and multiple power domain applications.