Hit your tapeout schedules with in-design signoff DRC
Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
EDA
Silicon photonics verification: Progress through adaptation
SiP promises advances in transmission speeds, bandwidth, accuracy and low power but verification requires careful evolution of existing tools.
Making sense of cloud EDA
How to carry out a sensible analysis of cloud EDA's potential, so you get the right tools and computational resources to deliver increasingly complex designs.
How ECAD-MCAD integration tackles the challenges of next-gen design
Creating strong links between the electrical and mechanical design domains is a leading enabler of digitalization.
Use machine learning and visualization to accelerate Liberty file verification
Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
Out-of-sync data issues in parallel design flows need automated design integrity checks
Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
May the Cloud be with you
How to unify your design team to defeat the dark side of board systems design.
How automated static checks help verify complex circuits for better performance and reliability
Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
Spiral in on silicon bugs in six formal steps
The best paper winner at DVCon 2021 details a comprehensive methodology for making the best use of formal verification for bug hunting
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