UltraSoC delivers trace for RISC-V
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Blog Topics
ARM DesignStart case study demonstrates scheme’s ease-of-use
ARM and Mentor describe a proof-of-concept project using free tools and IP to combine AMS and digital.
Triage without tears: improving debug’s most human challenge
Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.
Capacity shortages loom if 2017 growth repeats
If current market trends persist, shortages in wafers are likely to follow, hurting the ability of some companies to ship silicon and boost the prices for those who can.
Codasip updates processor-architecture tools
Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
Demand for better video, audio prompts HDMI 2.1 IP push
IP provides key building blocks for building better video and audio playback devices using HDMI 2.1
Synopsys integrates Helic’s EM tools to tighten margins on mixed-signal, analogue and RF SoCs
Better integration of EM modeling and analysis tools with Synopsys' Custom Compiler should enable tighter design margins
Ceva dedicates hardware to deep learning
Ceva has developed its first processor architecture aimed squarely at deep learning.
The best in PCB design during 2017
Read some edited highlights from the most successful companies in Mentor's 2017 Technology Leadership Awards.
Watch out for layout effects on finFET reliability
As geometries have shrunk, layout-dependent effects in CMOS have become ever more problematic. They are not just popping up in performance but reliability and aging effects as one IEDM presentation showed.