TSMC Altera heterogeneous integration is cool but is it 3D?
This looks more like 2.5D silicon interposer-based technology to us, though it is a major and necessary advance
Blog Topics
The return of the ‘custom’ embedded OS
Colin Walls of Mentor Graphics on a significant surprise in UBM’s latest market survey
Showtime! SNUG and U2U previews
We look at the upcoming Synopsys and Mentor Graphics user meetings in Santa Clara.
CPTF notebook: The end of planar
It's time for everyone to start thinking about how to handle the incoming finFET age.
Japan one year on: a need to rebuild exposed?
Beyond the earthquake, analyst IHS says the tragedy revealed systemic problems with an aging semiconductor fab base
DATE 2012: Coverage roundup
This page brings together all of our coverage from Design Automation and Test in Europe 2012 in Dresden, Germany.
DATE notebook: Aldec builds in more support for VHDL methodology
Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
DATE notebook: Constraints smooth path for FPGA synthesis
Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.
CPTF notebook: From restricted to ‘proscriptive’ design rules
Ever increasing lithography challenges mean the next generation of design rules may concentrate on telling you just what you can rather than what you cannot do.
CDN Live: Cadence’s Encounter revamp collates innovation
Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.