March 20, 2012
Beyond the earthquake, analyst IHS says the tragedy revealed systemic problems with an aging semiconductor fab base
March 16, 2012
This page brings together all of our coverage from Design Automation and Test in Europe 2012 in Dresden, Germany.
March 16, 2012
Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
March 15, 2012
Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.
March 15, 2012
Ever increasing lithography challenges mean the next generation of design rules may concentrate on telling you just what you can rather than what you cannot do.
March 15, 2012
Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.
March 14, 2012
Old processes don't necessarily equate to old tools, panelists argued at DATE, especially when a lot of future work will be done on more-than-Moore, 3DIC technologies.
March 14, 2012
We round up the latest headline forecasts and performance data from the Global Semiconductor Alliance (GSA), manufacturers association SEMI and the Semiconductor Industry Association.
March 13, 2012
DATE panelists discuss three ways to tackle design complexity: by moving to higher levels of abstraction; by making more subtle use of existing synthesis strategies; and by better organisation.
March 13, 2012
The CTO of one European design house wants better acceleration features from analog design tools, not automation that overrides their judgement.