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Cadence Design Systems has issued a call for papers for the European leg of its CDNLive of events for 2014. The deadline for the Silicon Valley event is also looming: the call closes mid-November 2013.

Silicon Labs is aiming at Internet of Things applications with an ARM Cortex M0+-based MCU family with encryption engine and low-energy DAC for biasing analog circuitry.

For the new web TV program Unhinged, Brian Fuller talked to venture capitalist Jim Hogan about the future of mixed-signal and the past of EDA.

In a keynote at the Intel Developer Forum, CEO Brian Krzanich said the company would start making 14nm processors by the year end and confirmed intel would license SoC designs to be fabbed by other companies.

Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.

ARM and Synopsys both plan to make inroads to the internet of things with their IP strategies.

A Japanese government-funded project has become the basis of a standard proposed by the Multicore Association that may provide a better way of supporting development for multicore systems.

Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.

Graphics chipmaker nVidia has said it plans to license as IP cores some of its technology in the hope of building up a customer base among other chipmakers and systems houses developing their own SoCs.

Design security is a major target for Microsemi’s update to its Igloo series of flash memory-based FPGAs, which add an ARM-oriented memory subsystem.