EDA Topics

A guide to emerging 3D integration techniques for ICs, including a look at various approaches, and some of the tools and standards issues involved.

Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?

How Cadence, Intel and Xuropa accelerated the semiconductor design process by squeezing 15% more capacity out of a virtualized server farm

Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.

Making a smooth transition to IJTAG, the scan-test strategy for IP blocks, without having to change your existing hardware.

Using a new design-partitioning tool and stacked-silicon interconnect FPGA to develop an ASIC prototyping platform that can be reprogrammed several times a day.

Characterizing standard-cell defect mechanisms helps improve IC testing

MCMM analysis is a technique intended to provide high-confidence results for timing closure and other metrics without performing exhaustive simulation of all possible IC conditions.

There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.

The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.