Vivado, inside the new Xilinx design suite
The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
EDA Topics
The physical design challenges of 20nm processes
Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
Physical verification of 20nm designs through integrated double-patterning analysis and repair
Finding and fixing double patterning problems in 20nm designs
System virtual prototyping
The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.
Virtual prototyping moves further into the mainstream
Carbon Design Systems' CTO Bill Neifert argues that his company's deal with Samsung sends a clear signal, whether or not you're one of his customers.
Moving to advanced reliability verification
Shrinking process nodes, rising power efficiency goals and burgeoning device functionality are stretching existing DFR techniques to their limits. This scalable methodology looks to address the shortfall.
Critical tools for 20nm design
A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
Clock domain crossing
IC designs with multiple clock domains are now commonplace. They make it possible to optimize for power by varying clock frequency and voltage as well as for timing by removing the need to distribute a single, low-skew clock to all parts of a design. The problem is that the use of multiple clock domains introduces […]
Getting ready for 20nm
Antun Domic of Synopsys tackles the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
Verification challenges require surgical precision
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.