EDA Topics

More than half of design companies claim to use ABV but many have yet to deploy full methodologies.

Building a prototype SoC in one or a set of FPGAs can aid field trials, software development and hardware/software integration. But it's not easy, so the decision to go ahead needs careful consideration.

Verification IP is becoming an increasingly important component for system design due to the rapid proliferation of new protocols and interfaces, chiefly driven by mobile comms.

How SystemC enables system modelling at higher levels of abstraction, and the creation of virtual platforms.

It may be necessary to move to three-dimensional 'FinFET' transistors for future process nodes, but what impact will this have on circuit design?

Fully depleted silicon on insulator (FD-SOI) transistor architectures may offer speed and power advantages, at the cost of a shift to non-standard substrates.

Logic glitches in asynchronous clock domain crossing paths can arise even when synthesis tools declare a design’s RTL and gate-level netlists equivalent. This article describes Real Intent’s approach to capturing them.

Root-cause analysis of detected errors is a key design step. Debugging can take more than half of the verification effort. Vennsa’s OnPoint automated debug technology has been integrated with Springsoft’s Verdi visualization platform to reduce cost and uncertainty.

An evolved ESL-to-RTL methodology flow addresses the ‘discipline gaps’ between software and hardware engineering by using three system level-based software-hardware verification steps. The strategy is already available in TSMC’s Reference Flow 12.

This two-part article discusses the verification requirements of the RTCA DO-254 design assurance guidelines, including advanced methods for use on class DAL A/B designs. The first part provides a general overview. It also explains the original intent behind the concept of 'elemental analysis', how it is typically satisfied today with code coverage, and the limitations [...]