2.5D-IC, 3D-IC, and 5.5D-IC – stacked-die integration
Faced with a slowdown in the rate at which device integration in two dimensions is improving, IC designers are now beginning to think about moving into the third dimension in order to keep packing more functions into these same volume. Although there is some confusion about terminology, 2.5D-IC, 3D-IC and even what some call 5.5D-IC design is becoming a reality, with companies such as Xilinx applying the technology to the top end of its FPGA family.
Drivers for 3D integration
For years the IC industry has been driven by Moore’s Law – the notion that by regularly reducing the minimum dimensions of its manufacturing processes, the functionality that fits on a single die will double every 18 to 24 months. While this remains true, as minimum dimensions have shrunk from 65 to 45 to 28 and now to 20nm, it has become increasingly difficult to design with those processes, and increasingly expensive to manufacture them. The upcoming shift to 20nm is likely to introduce new difficulties, such as a shift to non-planar finFET transistor structures, more complex double-patterning lithography for critical layers, and perhaps even new substrates.
As electronics becomes more pervasive, designers also want to integrate more diverse functions in their chips: think of a smartphone with its high-speed digital logic, analog, mixed-signal and RF sections, MEMS actuators and variety of sensors. Integrating these functions in a single process may be difficult or impossible, and if it can be done the performance compromises and yield issues may mean it doesn’t make sense to do so anyway.
Returning to the smartphone example, the bandwidth requirements between processor and memory, for example for handling video streaming, are increasing so fast that they challenge the traditional interconnect schemes used to connect packaged chips. Power consumption and management is also an issue, and ensuring that a system’s major bus lines are as short as possible by packing components together more tightly helps with this.
[Marco Casale Rossi, senior product marketing manager for 3D IC at Synopsys, provides a useful industry view on this topic in his blog on the advantages and challenges of 3D integration.]
Companies have been trying to increase functional integration more quickly than Moore’s Law or circuit performance requirements have allowed for years, hence the proliferation of interconnect schemes such as multi chip modules, silicon in package and package-on-package schemes. The shift to a 3D-IC approach is supposed to lead to a more profound level of integration, as die are stacked on die or on silicon interposers, which are effectively silicon PCBs.
3D integration schemes
Here are a few of the common approaches to 3D integration:
In 2.5D-IC designs two or more die are placed face down and side by side on a silicon interposer. Microbumps on the active surface of the die, perhaps repositioned by a redistribution layer, connect to pads on the surface of the silicon interposer. Connections from those pads, either directly or through another redistribution layer, connect to TSVs which pass through the interposer substrate and connect, again with the option of a redistribution layer, to the package.
Active die are stacked one on top of another and interconnected vertically using through-silicon vias (TSVs). The technique can be used with a stack of similar die (the homogenous approach), for example to build ‘memory cubes’, stacks of pure memory die with the controller logic on a separate die at the bottom. It is also being developed for use with a mix of different die (the heterogenous approach), although this is more complex and challenging. Here’s a couple of approaches to 3DIC integration.
Face to face
Two die are connected face to face using microbumps.
The lower die also has TSVs through its active layers and substrate to metallisation on its back surface, which acts as a redistribution layer using pads on to which C4 bumps are laid to connect it to the package substrate.
Face to back
Two or more die are placed, one on top of the other, with their active areas facing downwards. The lower die has metallisation on the back of its substrate, and microbumps are used to connect the top die to this metallisation. TSVs that pass through the lower die’s substrate connect the microbumps on the top die, via the backside metallisation, to the active area of the second die. C4 bumps on the surface of the active area of the lower die connect the assembly to the package substrate.
Although this approach has its advantages, the fact that the TSVs pass thorough the active areas of the lower die means that designers have to take more care over managing potential interactions between the TSVs and adjacent planar signals and circuitry, and routing around them.
In both cases the lower die is usually thinned, to about 50µm.
It is easy to imagine lots of variants upon these approaches, which brings us to:
This term was mentioned, partly as a joke, at a DAC panel in June 2012. It describes an integration approach which connects one or more 3D-IC stacks to a 2.5D-IC silicon interposer. One way in which this might be used would be to build a high-bandwidth memory/processor hybrid using a memory cube and a processor on an interposer.
Whether the term becomes established or not, its use reflects the richness of options available with these 3D integration technologies – and therefore the challenges for designers and the tool vendors that support them as they explore these options.
At another panel on 3D-IC technology at DAC in June 2012, IBM Fellow Subramanian Iyer pointed out that the current approaches to 3D–IC are really about creating new packaging options: “We haven’t achieved integration at the circuit level in the vertical dimension – this takes a wafer-level bonding approach using SOI-like processes.”
Taking such an approach would lead to “formidable challenges” in wafer alignment and yield management.
“It requires radically new thinking about how one can accept high levels of defects and yet [the system] still works. It requires new thinking at the system and software level.”
Intel Fellow Shekhar Borkar added: “This has to happen because die stacking is so expensive.”
Constituents of 3D-IC technology
Bumps and balls
One of the things that 3DIC technology does is help match the spacing between interconnect scheme on two different manufacturing technologies, for example between that of an IC and that of a PCB. In 3DIC technology, there are a number of these transitions. Starting at the outside of the package and working in we find:
Ball grid arrays
A package-level interconnect that connects a packaged device to a PCB
C4 (controlled collapse chip connection) bumps
A relatively coarse-grained interconnect scheme, made up of solder balls set out on a grid at a pitch of around 180µm. The grid pitch hasn’t changed much in years.
Used to connect a bare die to a package.
Smaller solder balls, set out at a pitch of as little as 10µm, that can be used to connect die face to face.
Through-silicon vias (TSVs) use IC etching technology to cut a hole from the active area on top of a die right through the substrate to its backside. The TSVs are then filled with copper or tungsten to make an electrical connection from the circuitry on the top of the die to its backside.
A TSV might have a diameter of 12µm and be laid out on a 180µm pitch. Because it takes a relatively long time to fill the TSV with the connecting metal, the substrate is often thinned, sometimes to just 50µm.
One challenge with TSVs is that they bring off-chip interconnections right into the heart of the active area of a die. This means that designers will have to incorporate ESD protection into the heart of their designs.
Designers may also have to cope with possible mechanical stress issues induced in the active area by the presence of TSVs, although some have already explored this issue and aren’t finding it a problem. Research presented at IEDM in December 2012 suggests the problem may be limited, but that the impact on adjacent transistors could vary depending on their orientation relative to the TSV.
Redistribution layers consist of metallisation on the surface of a die, either on its active face or on the back of the substrate, which is then patterned to redistribute connections from one part of the die to another, or to overcome a mismatch in the pitch of two interconnection technologies. Redistribution layers have landing bumps on which micro bumps can be formed to make connections.
Silicon interposers can be thought of as silicon PCBs. They are usually built in a trailing-edge mainstream IC process, but have no active elements. For example, TSMC offers a silicon interposer technology built in a 65nm process with four layers of metal interconnect.
FPGA company Xilinx has used this technology to build its latest generation of high-capacity devices. They feature two or four FPGA die, configured as rectangular slices, on what Xilinx calls a stacked silicon interconnect. Using four 500,000 logic-cell die offers better IC manufacturing yield than building one 2 million gate die, although assembling the die onto the interposer must have a yield cost of its own. The Xilinx approach also offers opportunities for heterogenous integration: one variant of the device family incorporates 28Gbit SERDES interfaces that are built on separate die and then mounted on a shared interposer.
The Virtex-7 H580T uses a silicon interposer to put 28Gbit/s transceivers on separate die from the core FPGA fabric (Source: Xilinx – click image to enlarge)
Silicon interposers are likely to have redistribution layers on front and back, and to use TSVs to bring power, signal and ground connections through the interposer die to package connections (the interposer is put between – interposed – the raw die and the package).
Although silicon interposers offer the opportunity to create rich interconnect resources between multiple die at the same signal level as on-die interconnects, handling large interposer die that have been thinned to enable fast TSV fill presents a challenge, although TSMC seems to have found a way of doing this.
There are design issues too – signals travelling over the interposer are likely to represent very long nets, and so will have an impact on timing. Such long nets are also likely to suffer signal integrity issue,s so it may be necessary to find ways to create shielding and ground planes within the interposer.
The relatively large silicon area of interposers may also prove a temptation to designers, who will start to incorporate active elements in the substrate and so complicate design flows.
Because building 3DIC devices demands insights into process technology, IC design and packaging techniques, there is a host of standards issues need to be resolved if the techniques is going to be widely used. These include, but are not limited to:
- EDA tools for 3D development and verification
- interposer models
- chip to chip interface standards
- DFM rules for TSVs, micro bumps
- thermal budgets
- test hardware and microprobing
- known-good-die methods
- self-test strategies
Fortunately there are plenty of existing standards bodies and standards that are relevant, or which could be adapted or extended for 3D-IC.
For example, JEDEC already has a standard for wide I/O mobile DRAM, which enables the use of TSVs to build memory cubes. Benefits of using the standard should include higher bandwidth to memory, smaller form factor and lower power consumption.
Meanwhile SEMI, the manufacturing body, has produced a standard way of describing the measurements of a TSV.
Standards body Si2 is trying to pull together existing and evolving standards through its 3D technical advisory body (TAB).
Speaking at a panel at DAC in June 2012 Riko Radojcic, a director of engineering at Qualcomm and chair of the open 3D TAB at SI2, said: “Standards are vital for facilitating hand-off from one part of the supply chain to another. For this to happen quickly we need broad-brush participation from the industry.”
Among the initiatives underway at Si2 are the development of 3D design exchange format standards, to enable intelligent stack design, considering issues such as power dissipation, thermal management, signal integrity, physical verification and design for test.
There are also efforts to try and understand how a designer could communicate the overall stack design intent and constraints.
“We’re looking for a standard that will facilitate information flow between design teams,” said Radojcic.
Other panellists listed short-term needs including well-qualified Spice models for micro bumps, interoperability with existing toolsets and the consolidation of best practice in 3DIC design.
Power modelling will also be important, because as process nodes shrink and slew rates rise inductive noise is rising, while noise margins are falling because of lower supply voltages. Designers will need simplified circuits that can model loads and parasitics to enable stacked die design and verification.
Over the longer term, designers want a better way to do pathfinding, that is exploring the wide variety of design options that 3DIC technology brings them, and a data exchange format for chip/package co-design.
Responsibility for sorting out a lot of these issues will fall in the tool vendors’ lap. As Alex Samoylov, vice president of engineering at Invarian, said during the same panel: “What do you need to do to turn a 2D physical design kit into a 3D physical design kit?”
3D-IC design touches on so many areas of chip design that tool suites are going to have to be updated in areas including:
- circuit design and schematic capture for redistribution layers, interposer signal routing, shielding and power
- place-and-route support, including TSV, microbump, redistribution layer and signal routing, power mesh creation and interconnect checks
- design-for-test for stacked die and TSV
- integrated memory test, diagnostics and repair systems
- parasitic extraction support for TSV, microbump, interposer RDL and signal routing metal
- circuit simulation for multi-die interconnect analysis
- thermo-mechanical stress analysis of TSVs and microbumps in multi-die stacks
- physical verification (LVS, DRC)
- extended design rule checking
- chip-level functional verification
- static timing analysis
- IR/EM/SI and other electrical analysis
- assembly and yield
What is likely to be much more challenging, though, is to upgrade existing tools and methodologies so that they can handle multiple process technologies.
Steve Smith, senior director of 3DIC strategy and marketing at Synopsys, said at DAC: “The die and the interposer are likely to be on different technologies and so you will need multi-technology-aware tools. For example, for extraction, we’ll have to extract each element separately and then concatenate them to create a single design file.”
Michael Jackson, vice president of Physical Implementation R&D at Synopsys, has written a useful look at the current state of tools development.
Samta Bansal, product marketing, applied silicon realisation, strategy and market development at Cadence Design Systems, said at DAC: “The system needs to handle heterogenous process nodes, it needs to understand TSVs, have updated routing strategies and a database to handle heterogeneous processes. It sounds like an evolution but it actually takes a lot to do.”