When good DFT goes bad: debugging broken scan chains
Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
The process of proving the system is working and performing optimally, under all application and environmental conditions, has become too inefficient and difficult for existing methodologies. Traditional methods for addressing post-silicon requirements have reached the point of diminishing returns. What was once an exercise of designing, implementing and verifying 25,000 to 50,000 gates of instrumentation […]