EDA Topics

Using hierarchy and improved constraints management to accelerate static timing analysis at 20nm and below.

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?

CSR used a customized approach to automated dummy fill layout for AMS to address layer density and device matching issues in standard flows aimed at digital SoCs.

The business case behind how virtual prototyping speeds development, improves hardware and software quality, and improves ROI.

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies

An exclusive extract from Cadence Design Systems' Mixed-Signal Methodology Guide provides an excellent overview of its discrete topic and a flavor of the book as a whole.

Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.

How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine