February 9, 2012
A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy. Here's what’s new in the proof-of-concept simulator, and how you can participate to refine the Accellera Systems Initiative’s work for standardization.
January 29, 2012
Transaction-level modeling (TLM) describes a system by using function calls that define a set of transactions over a set of channels.
January 24, 2012
Functional logic errors remain a significant cause of project delays and re-spins. One of the main reasons is that two important aspects of verification environment quality—the ability to propagate the effect of a bug to an observable point and the ability to observe the faulty effect and thus detect the bug—cannot be analyzed or measured. [...]
January 24, 2012
The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.
January 23, 2012
Virtual prototyping is not a new technique, but the advent of transaction-level modeling and an increased focus on seven key requirements for their effective use means that today's versions are much more broadly applicable and comparatively future proof.
January 16, 2012
Double patterning provides an alternative to using EUV lithography – making it possible to implement ICs on sub-28nm processes.
January 16, 2012
The IEEE Unified Power Format (UPF) standard is intended to support low-power designs that use switchable power states and power islands.
October 19, 2011
The launch of a broad-based IDM/foundry consortium that is to prepare for the shift to 450mm wafers already offers some hints as to the future shape of chip manufacturing and the planning demands it will impose on all design managers in the near future. The game is shifting from pay-for-capacity to outright pay-to-play for those [...]
August 25, 2011
Belgian research institute Imec describes, for the first time, the selective chemical vapor deposition (CVD) of germanium-tin (GeSn) in a production-like environment using commercially available Ge and Sn precursors. The resulting GeSn layers with 8% Sn are defect free, fully strained and thermally stable for temperatures up to 500°C. The technique is used to implement [...]
August 23, 2011
By the time a serious lithography-related problem is identified at the fab, it is too late in the design process to make simple layout changes. To avoid or reduce design delays, Infineon Technologies uses lithography simulation to detect weak points in a layout and analyze the effect of lithography on the design’s electrical performance. Its [...]
