Are advanced designs only possible at emerging process nodes?
Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.
IC Implementation
Patterning choices loom for 10nm and beyond
It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
Using HAPS to streamline IP to SoC integration
The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Better management of timing closure and optimization
How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.
How high-level synthesis helps optimize low power designs – Part Two
Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
FinFET parasitics come under control
Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
Improving performance through better delay estimation of sub-32nm interconnects
Better delay estimation of sub-32nm interconnects, in which resistivity varies up to 100x between layers, helps Cavium improve overall performance and get ready for even denser processes
How high-level synthesis helps optimize low power designs – Part One
Going inside HLS' basics shows how it can deliver power savings over 50% for some applications.
The requirements for complete RTL signoff
Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Power grid analysis for 2.5D and 3D IC systems
PGA has been IC-centric for mainstream 2D configurations. It must become system-centric for 2.5D and 3D systems.
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