An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.
Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
The basics of USB 3.2, how to implement it in an SoC, and how USB Type-C connectors and cables are used in USB 3.2 systems.
How the digital twin can fuel automotive verification flows impossible in the real world.
As AI becomes pervasive in computing applications, so too does the need for high-grade security in all levels of the system.
Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
Machine-learning strategies for embedded vision are evolving so quickly that designers need access to flexible, heterogenous processor architectures that can adapt as the algorithms evolve.
Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
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