Expert Insights

Ashish Darbari  |  January 7, 2019

Doc Formal: Introducing the ADEPT FV flow

Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
Rahul Chirania  |  December 3, 2018

Verifying clock domain crossings in UPF-based low-power SoCs

The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:   |  
Morten Christiansen  |  November 5, 2018

Understanding USB 3.2 and Type-C

The basics of USB 3.2, how to implement it in an SoC, and how USB Type-C connectors and cables are used in USB 3.2 systems.
Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , ,   |  Organizations:   |  
Philip Vanness  |  October 26, 2018

8.8 billion miles to verify

How the digital twin can fuel automotive verification flows impossible in the real world.
Dana Neustadter  |  October 16, 2018

Why AI needs security

As AI becomes pervasive in computing applications, so too does the need for high-grade security in all levels of the system.
Topics: IP - Selection  |  Tags: , ,   |  Organizations:   |  
Allen Watson  |  October 3, 2018

An open-source framework for greater flexibility in machine-learning development

Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
Gordon Cooper  |  September 23, 2018

Flexible embedded vision processing architectures for machine-learning applications

Machine-learning strategies for embedded vision are evolving so quickly that designers need access to flexible, heterogenous processor architectures that can adapt as the algorithms evolve.
Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , ,   |  Organizations:   |  
Gandharv Bhatara  |  September 11, 2018

EUV’s arrival demands a new resolution enhancement flow

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Topics: EDA - DFM, - EDA Topics  |  Tags: , , , , , , ,   |  Organizations: , ,   |  
Ashish Darbari  |  August 14, 2018

Doc Formal: Achieving exhaustive formal verification of packet-based designs

Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
Dina Medhat  |  August 13, 2018

Managing waivers in reliability verification

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.

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