Arm

February 18, 2016

ARM, Ceva aim at multi-carrier modems

ARM and Ceva have both aimed at the need for to juggle control code and DSP in the upcoming LTE-Advanced and 5G with their latest processor core architectures.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , , , ,   |  Organizations: ,
December 11, 2015

IEDM keynote: cost scaling will swap architectural changes for area

According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations:
November 11, 2015

UltraSoC adds CoreSight and Ceva debug support

UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations: , ,
November 10, 2015

ARM ports Trustzone down to Cortex-M

ARM is bringing the Trustzone security architecture to future Cortex-M processor cores, combining that with a version of AHB that will recognise the difference between secure and non-secure transactions.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations:
October 29, 2015

ARM targets cache-coherent GPU computing with CoreLink addition

ARM has developed a version of its CoreLink on-chip interconnect IP intended to support systems based on its big.Little processors combinations that need a cache-coherent GPU connection with lower latency and higher peak throughput.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations:
October 20, 2015

ARM snaps up Carbon model IP for prototyping

ARM has moved back into system-level modelling with the decision to buy the tools and models developed by Carbon Design Systems
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations: ,
August 6, 2015

Flow exploration key to finFET network processor implementation

Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , ,   |  Organizations: , ,
July 30, 2015

10nm flow reveals complexity of finFET design process

Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , ,
June 10, 2015

TSMC adds Cadence and Imagination subsystems for IoT

Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.
June 9, 2015

COMPUTEX 2015: Wrap II – New customers

Electronics design needs to cope with a combination of major brands and tiny start-ups looking to exploit its skills even where their resources are thin.
Article  |  Topics: Commentary, Conferences, Blog - EDA, IP, PCB  |  Tags: , , , ,   |  Organizations: , , , , ,

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