SystemC materials move to Apache 2.0 license
Accellera has moved to an Apache 2.0 open-source license for all of the supplementary materials for its SystemC library.
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Chinese dates set for Asia-Pacific editions of Mentor Forum
Wally Rhines headlines as keynote at free technical events set for Shanghai on August 30 and Beijing on September 1.
Cadence adds floating point to Fusion
Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
IEDM alters schedule to keep abreast of process updates
The International Electron Device Meeting has pushed back the deadline for its papers to get the latest developments in process and device design into the December conference.
EEMBC looks into heterogeneous compute
EEMBC has turned its attention to heterogeneous computing with plans to create a new set of benchmarks.
Mentor’s PADS family extended for AMS, DDR and electrical DRC
Mentor Graphics has added four new units to its PADS PCB family addressing increasing complexity in mainstream design.
RC extraction from ‘virtual fab’ models may speed PDK availability
Electrical analysis facility does RC extraction on virtual fab models, accelerating the availability of early PDKs for new processes
2D tools adapt to create smaller monolithic 3DIC designs
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
ARM accelerates POP deployment for Cortex-A73
A faster implementation program for the POP support IP for ARM's cores has delivered a 16nm finFET package for the Cortex-A73 shortly after the core's Computex launch.
Analyzer merges constraints for multiple timing modes
Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.