The physical design challenges of 20nm processes
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
double patterning
TSMC updates reference flows for 20nm and CoWoS
TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).
Event alert: TSMC Open Innovation Platform
With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
Getting ready for 20nm
Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
Aart de Geus on the changing face of EDA
The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.
DAC 2012: STMicro, Cadence, GlobalFoundries in 20nm AMS claims
The troops will be out in force next week to claim progress on 20nm AMS design flows that take manufacturability into account.
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