UltraSoc donates trace format to RISC-V group
UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
TSMC encapsulates CoWoS for supersized SiP
TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company’s CoWoS2 SiP technology.
Samsung 7nm uses EUV and split fin widths to push speeds
EUV and fin optimization help build Samsung’s upcoming 7nm process, the company discloses at the VLSI Technology Symposium.
DAC 2017 preview: Plunify
Plunify will demonstrate its new Kabuto tool that recommends RTL fixes for FPGA designs at the Design Automation Conference.
DAC 2017 preview: Baum
Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.
DAC 2017 preview: Austemper Design
Local EDA vendor Austemper will be demonstrating a comprehensive functional safety design tool suite in Austin next week.
Early access view of portable-stimulus standard released
Accellera has released an Early Adopter version of the upcoming Portable Stimulus Specification.
Microsemi builds Windows IDE for RISC-V
Semiconductor supplier Microsemi has used the Eclipse open-source IDE platform to develop a Windows-based toolchain for CPUs that supports the RISC-V instruction set.
DAC 2017 preview: Breker
At a DAC that will feature the arrival of the Accellera portable stimulus standard, Breker will demonstrate its implementation of the Early Adopter release of the specification.
Smart code editor adds SystemVerilog support
Sigasi has added support for SystemVerilog to its Sigasi Studio tool, which uses a built-in parser to perform more reliable syntax highlighting and error checking