Technical Newsletter #3: Site updates, DATE highlights, CPTF, CDN

By Luke Collins |  No Comments  |  Posted: March 21, 2012
Topics/Categories: no topics assigned  |  Tags:

Headlines

In this issue, we first chart trends from Europe’s leading design conference, as well as from the Common Platform Technology Forum and CDNLive in the Valley. You can then scroll down to also see descriptions of the latest technical content we’ve posted and our most recent blog coverage.

DATE 2012

  • EDA for the rest of us: DATE delegates put major vendors on the spot to ask what they’re doing for the bulk of us who are not working at the most advanced process nodes.
  • Design complexity: A DATE panel placed the emphasis on a combination of higher levels of abstraction, more subtle synthesis and better organization.
  • Accelerate analog: Productivity must get above the one-device-per-manday plateau. A good start would be better scripts.
  • Automotive directions: Find out what Robert Bosch sees as the current drivers for in-vehicle electronics.
  • Ecosystems or bust: The foundry sector must move beyond contract manufacturing through ever broader collaboration.
  • Europe’s server dream: The EU wants to reinvigorate the region’s HPC sector and sees an opportunity in the cloud.

 

CPTF/CDNLive

  • Design rules: From ‘restricted’ to ‘proscriptive’, from what you can do to what you can’t.
  • Cadence Encounter: Innovations that helped deliver the first 20nm Cortex A-15 test chip come to the wider market.

 

New technical articles

  • Texas Instruments: How Wolverine slashes MCU power consumption by 50% and how you can exploit it.
  • Vennsa/SpringSoft: When debug can take up more than half of your verification, analyzing the root-causes of detected errors needs to be done quickly and accurately. The two vendors have integrated their OnPoint and Verdi suites to enable just that.
  • Mentor Graphics: The GNU project has delivered fantastic open source technology for embedded Linux development, but there are still risks to be minimized.
  • Real Intent: Logic glitches in asynchronous clock domain crossing paths can arise even when synthesis tools declare the RTL and gate-level netlists equivalent. RI says it can catch them.
  • Nujira: Can a technique that’s more than 50 years old seriously reduce mobile basestation power consumption? This article puts the case.

 

Viewpoint

Welcome to our third newsletter. It’s been a busy fortnight with DATE, Cadence’s user conference CDNLive and the Common Platform Technology Forum. We’ve also begun to populate the site with more technical content as part of our move from being a quarterly journal to a continuously updated technical resource.

I just wanted to briefly bring your attention to a few other things of note. First, we’ve added two new article sections.

TDF Circuits is a new feature that takes a graphical view of one section of a particularly innovative design. Our first subject is BASIC, a highly efficient technique for reducing noise artifacts in disposable healthcare monitoring systems from IMEC, KU Leuven and the Samsung Advanced Institute of Technology.

By the numbers is a new subset of our blog newsfeed that collates some of the latest research data, so that you can get an overview of several metrics at once and a broader sense of industry trends. Our first entry looks at the latest sales, fab equipment and VC investment numbers.

Finally, as you know, we worked closely with the three companies in the Common Platform foundry alliance in the run-up to its physical Technology Forum earlier this month in Santa Clara. Having at that time been attending DATE, I’ve found it very useful that the alliance has posted plenary sessions and several exclusive online-only presentations as part of a Virtual Technology Forum that will be available all year.

I’d particularly guide you to the excellent presentation from IBM’s Gary Patton on the roadmap for 14nm and beyond. It’s a genuinely informative and detailed description of the challenges ahead and what Big Blue sees as some of the potential solutions. But there’s much more useful content you can access, if you weren’t able to make it on the day.

Meanwhile, we continue to develop Tech Design Forum to make it the most informative and practical resource for system design. In the next few weeks, we’ll be rolling out more of our Guides that will eventually underpin the entire site, and make it much easier for you to access the right kind of technical information and commentary quickly. As ever, we welcome your feedback on these and other features. Just click on the ‘Interact’ button in the right-hand column.

Luke Collins

Now online

Do you want to contribute or send material to Tech Design Forum? We’ve updated our guidelines.

Guest blog: Colin Walls on the return of the custom OS in embedded

Low power: ARM gets ‘surprise’ savings by storing instructions in the L1 cache

VHDL verification: Aldec enhances Riviera-Pro to support the OS-VMM methodology

FPGA synthesis: Blue Pearl Software brings timing analysis to PLDs through Synplify Pro hooks

Thermal analysis: Docea Power helps package and floorplan assessment

DFM: GlobalFoundries’ DRC flow adds Calibre pattern recognition

TDF Circuits: BASIC overcomes noise for portable medical devices

Competitiveness: Did the 2011 earthquake expose systemic weaknesses in Japan’s chip industry?

By the numbers: The latest data on VC investment, chip sales and fab spending

User conferences: Previewing the Silicon Valley editions of Synopsys’ SNUG and Mentor’s User2User

Newsletters: Issue #2: IBM on beyond 14nm, GlobalFoundries on 28nm, Mentor on double patterning

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors