In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography has been explored and documented in the literature.1-5 It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, […]
The OASIS working group was first initiated in 2001, published the new format in March 2004, which was ratified as an official SEMI standard in September 2005. A follow-on initiative expanded the new standard to cover the needs of the mask manufacturing equipment sector with a derived standard called OASIS.MASK (P44) that was released in […]
Computational lithography has become an integral part of design since the 130nm process node. New techniques continue to be developed to extend the steady node shrink year after year.
By adding a second deflector-aperture stage to the electron beam column of a vector shaped mask writer in which the aperture has the shape of a cross, one gains the ability to print a parameterized “L-shaped” exposure. This is the most modest generalization of the shot shape in such machines that retains the current paradigm […]
With rapidly shrinking feature sizes, full chip robust Optical Proximity Correction (OPC) will take longer due to the increasing pattern density. Furthermore, to achieve a perfect OPC control recipe becomes more difficult. The critical dimension of the design features is smaller than the exposure wavelength, and there is only limited room for the OPC correction. […]
One of the major problems in the RET flow is OPC recipe creation. The existence of numerous parameters to tune and the interdependence between them complicates the process of recipe optimization and makes it very tedious. There is usually no standard methodology to choose the initial values for the recipe settings or to determine stable […]
During optical proximity correction (OPC), layout edges or fragments are migrated to proper positions in order to minimize edge placement error (EPE). During this fragment migration, several factors other than EPE are a part of the cost function for optimal fragment displacement. Several factors are devised in favor of OPC stability, which can accommodate room […]
Nanotechnology's economic potential will only be harnessed through more basic research, according to a new report from the NSF. Paul Dempsey reports.
As part of our nanotechnology focus, we look at the prospects for graphene and carbon nanotubes in electronics. Paul Dempsey reports.
Morris Chang was in on the ground floor of IC innovation at TI and remains there today as chairman of TSMC. Paul Dempsey reports.