The growing verification challenge, and how to address it by coordinating multiple debug strategies.
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
How Cadence, Intel and Xuropa accelerated the semiconductor design process by squeezing 15% more capacity out of a virtualized server farm
Making a smooth transition to IJTAG, the scan-test strategy for IP blocks, without having to change your existing hardware.
This article describes various non-volatile memory (NVM) intellectual property (IP) alternatives with specific reference to their integration within system-on-chip designs targeting the 65nm process node and below. The article considers many of the strengths and vulnerabilities of these IP options, and then describes the tests that must be undertaken to ensure their long-term reliability, particularly [...]
New open software platforms can dramatically advance the way consumers interact with the Internet via their televisions and an expanding array of TV-like mobile devices. Ultimately consumers will be able to access websites that are fully optimized for the TV platform. Today, this experience is primarily delivered via widgets—containerized web pages or information portals that [...]
View All Sponsors