Enabling greater productivity and schedule predictability in IC design

Neel Desai is Synopsys product marketing manager for the Lynx Design System. He has over 18 years of EDA and semiconductor experience, including eight years as product marketing manager for Design Compiler. Neel received his BSEE from the University of Bombay, his MSEE from Pennsylvania State University and his MBA from Santa Clara University.

The semiconductor industry is a hard taskmaster. The basic rule is that the next generation of a chip design will be more complex than the last, and yet should be delivered at least as quickly, if not quicker, without compromising performance or power consumption.

With the introduction of double-patterning lithography (Guide) and device architectures such as finFETs (Guide) at the 20nm node, moving between process nodes is becoming more difficult. This is creating two challenges for the design community: coping with the extra complexity of process nodes at 20nm and below; and, for those who do not want to make the transition yet, squeezing greater utility out of mature processes.

All the while, the pressure is on design managers to achieve more with their existing resources, even as the design and physical verification tasks become more complex with increased functional integration levels and the inclusion of increasing amounts of software on chip.

To cope with these issues, design managers need tools that can help them manage complex SoC design projects, monitor their progress and forecast their outcomes. This involves coordinating the design efforts of multiple engineers and analyzing massive amounts of data, to achieve the fastest and most predictable tape-out possible.

In response to this challenge, Synopsys offers the Lynx Design System, a chip design environment that provides the kind of standardized structure, automation and data analysis that design managers need to help them track complex projects. Lynx includes an open, customizable, production-proven RTL-to- GDSII design flow, and adds intuitive GUI automation for its set-up, execution and editing. The availability of pre-tested flows reduces the risks associated with migrating to a new process node. It also captures and presents key project metrics on demand, so that project managers can track design development and measure progress easily.

Lynx can also help design teams that have been challenged to get more out of the in-use process node, rather than relying on a smaller process node to bring their required area and performance results. Lynx can be set-up so that different tool versions or tool switches can be applied at the task or flow level, enabling design engineers to quickly evaluate flow alternatives to squeeze more functionality out of their existing IP and process technology or migrate to new ones. This means that users can sometimes postpone the migration to a smaller process node, reducing risk and lowering cost.

Lynx also includes features that make it easier to deploy and validate technology-related IP. For example, Lynx Technology Plug-ins enables users to pre-validate technology files and IP libraries from any foundry or library vendor. Hard IP can be validated for use in the flow by performing standalone and interoperability testing with other IP blocks. These capabilities speed up the beginning of a project and improve the quality of designs when they reach the foundry, reducing time to market.

Along with automating the design flow, the Lynx Management Cockpit offers browser and client-based access to important project metrics such as the chip’s timing, cell utilization, clock skew, leakage power, and fault coverage, as well as system resources such as runtime, CPU and memory usage. Users can also add their own metrics. Having easy access to these metrics helps managers use their people and compute resources most effectively, and makes it easier to predict when a design will be finished.

Chip design is a constant battle against rising process and functional complexity on the one hand, and reducing time to market on the other. A design environment that includes the validation of IP, libraries and foundry technology data at the beginning of the process; support for standard yet adaptable design flows; and insights into key project metrics throughout can ease the job of getting chips out of the door and into customers’ hands.