Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
This article looks at some of the key architectural and implementation decisions Synopsys has made in developing a version of its HS series of licensable processor cores to serve the embedded Linux market
A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes
FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Will Ethernet become the dominant interconnect for automotive applications? A look at the market trends and standards, and how to use Ethernet IP and virtual-prototyping solutions in automotive applications.
How to use PCIe in low-power SoCs by swapping the standard PCIe PHY for M-PCIe, defined by MIPI for mobile use
The encryption chain for today's highly collaborative designs needs to be managed with care.
The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.
View All Sponsors