IP Topics

June 1, 2016
How Google and Qualcomm use HLS and HLV

How Google and Qualcomm exploit real world HLS and HLV

By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
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May 10, 2016
USB Type C connector

Implementing USB Type-C

A look at three design challenges for USB Type-C: implementing two SuperSpeed datapaths on a reversible connector; partitioning the design to support multiple USB Type-C variants; and partitioning the management software.
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April 12, 2016

Understanding the USB 3.1 protocol

A look at USB 3.1, which offers data rates of up to 10Gbit/s, and the way that the USB 3.1 protocol has changed to support this rate.
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March 24, 2016

True random number generators for a more secure IoT

An analysis of what it takes to build true random number generators that can provide a strong cryptographic basis for systems security, especially for IoT devices.
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March 21, 2016
Manuel Mota, technical marketing manager, Bluetooth IP, Synopsys

Enabling energy-efficient wireless IoT designs with Bluetooth Smart IP

A quick look at Bluetooth Smart and how it can be used to provide network connections in certain classes of IoT application.
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March 3, 2016

What’s cooking at the Flash Diner?

Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
February 22, 2016

Floorplanning complex SoCs with multiple levels of physical hierarchy

How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
February 18, 2016
RTL Floorplanning - Featured Image

How new RTL floorplanning techniques speed physical design

Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
February 10, 2016
Geoffrey Ying, director of product marketing, AMS group, Synopsys

Speeding AMS verification by easing simulation debug and analysis

How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
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January 22, 2016
Verification IP, Mentor Graphics, Jan 16, Featured Image

Easing the use of APIs for verification IP stimuli

How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.
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