We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
Moving part of all of a design flow to the cloud involves careful preparation and evaluation as there is no 'one-size-fits-all'.
Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
Knowledge, intelligence and optimization are key to managing the logistical disruption seen since the Covid-19 outbreak.
Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.
The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.
A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.
A look at the device types defined by the Compute Express Link (CXL) standard.
A look at the key protocols that control the Compute Express Link (CXL) standard for connecting CPUs and accelerators in hetereogenous computing environments.
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