Debugging complex RISC-V processors
RISC-V adoption is growing fast as is the ecosystem around the open-source core. Hardware and software are now vital for appropriate debug.
IP Topics
Improved power management and faster time to market?
We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
How to migrate SoC design to the cloud
Moving part of all of a design flow to the cloud involves careful preparation and evaluation as there is no 'one-size-fits-all'.
Give the people what they want: toward making 3D IC mainstream
Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
A three-phase strategy to master the supply chain tsunami
Knowledge, intelligence and optimization are key to managing the logistical disruption seen since the Covid-19 outbreak.
Formal verification for SystemC/C++ designs
Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
Resolving IP cell-name conflicts peacefully
One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.
How to use runtime monitoring for automotive functional safety
The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.
Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs
A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.
Introduction to the Compute Express Link (CXL) device types
A look at the device types defined by the Compute Express Link (CXL) standard.