A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.
A look at the device types defined by the Compute Express Link (CXL) standard.
A look at the key protocols that control the Compute Express Link (CXL) standard for connecting CPUs and accelerators in hetereogenous computing environments.
A guide to the emerging Compute Express Link (CXL) standard, which links CPUs and accelerators in heterogenous computing environments.
Using a hardware root of trust and a secure development lifecycle process to form the basis of a better approach to developing and implementing more secure complex SoCs.
Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.
This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.
The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
SoC suppliers building the key components for hyperscale data centres need access to the latest IP to handle functions such as PCIe, DDR5, cache coherency, NVMe SSDs, and the highest-bandwidth Ethernet implementations.
Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
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