cache coherency

Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.

This article looks at some of the key architectural and implementation decisions Synopsys has made in developing a version of its HS series of licensable processor cores to serve the embedded Linux market

This part illustrates the technique using examples addressing memory corruption, multicore systems and cache coherency with particular reference to watchpoints.

Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.