EDA Topics

FinFET processes and libraries are maturing, enabling designers to explore the best ways to take advantage of the capabilities of the new transistor design

Considering the issue of functional safety verification in automotive systems design, within the context of ISO26262

How to tune your scan pattern creation and application to cost-effectively match your test objectives.

How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.

Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.

Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.

Engineers developing an SoC for the automotive market have to show that it doesn’t have functional safety issues - even if the SoC enters an unexpected state. Here's how to tackle the safety verification task.

Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.

A look at how collaboration between design, process and tool development is becoming increasingly important to get the best out of the most advanced nodes.