Validating on-chip variation: Is your library’s LVF data correct?
Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
Verification
Doc Formal answers 11 key questions
The doctor was 'in' during last month's DVCon and here highlights some of the main issues in formal raised by delegates at the verification conference.
Accelerating the implementation of application-specific processors
Application-specific processors can provide high performance for specialised tasks at low energy cost.
Fast, accurate layout merging for SoC flows
How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
Low-power debugging made easy
UPF provides a useful way to describe the power-management strategies that should be applied to a design, but using it introduces a number of challenges during low-power debugging.
Create more flexible virtual sequences with Portable Stimulus
Virtual sequences are considered challenging to write and re-use. Learn how to overcome those issues with the new Portable Stimulus Standard in this DMA-based case study.
Doc Formal: Introducing the ADEPT FV flow
Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
Win on the fault campaign trail with formal
How formal verification for the ISO26262 automotive functional safety delivers the full activation, propagation, and observation in the form of proven and exhaustive results.
Verifying clock domain crossings in UPF-based low-power SoCs
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
Adding system-level, post-layout electrical analysis to HDAP design and verification
Adoption of high-density advanced packaging (HDAP) needs tools and supports to build designers' confidence in the emerging technology.
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