July 3, 2014
How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
June 30, 2014
Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.
June 15, 2014
Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?
May 29, 2014
A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
May 28, 2014
As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.
May 24, 2014
IC designers are becoming increasingly worried about the possibility of third parties inserting malicious 'trojan' circuitry into their ICs.
May 24, 2014
ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
May 19, 2014
The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
May 19, 2014
Verification coverage attempts to at least provide a partial answer to the question: "How do you know you are finished verifying?" It involves the combination of a number of techniques.
May 17, 2014
Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.