constrained random verification (CRV)

January 19, 2020
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Accelerate your UVM adoption and usage with an IDE

How an integrated design environment can help you overcome complexities within the Universal Verification Methodology and manage the size of the libraries within it.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations: ,
May 29, 2015
Mentor Graphics/Wilson Research Group Functional Verification Study

Smaller designs face greater risk of respins

Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
May 21, 2012

Where there’s a will… there’s a way to better VHDL verification

An overview of the Open Source VHDL Verification Methodology and two of the libraries it uses.

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