Intel

June 10, 2014
High-speed I/O eye diagram - thumbnail

Zeroing in on the problems of fast board-level interconnect

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
July 26, 2012
Cloud image

Optimizing cloud computing for faster semiconductor design

How Cadence, Intel and Xuropa accelerated the semiconductor design process by squeezing 15% more capacity out of a virtualized server farm
August 23, 2011

Parting of the ways

Intel says ‘trigate’—finFET to others—but depleted silicon-on-insulator also has its post 22nm supporters. Chris Edwards reports on the debate at 2011’s Semicon West.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,   |  Organizations: ,
June 1, 2008

Intel takes a new path from A to D

Justin Rattner will this year mark 35 years with Intel. His career with the technology giant has seen him collect numerous accolades, particularly for work in areas such as high performance computing (HPC). He was Intel’s first principal engineer and was its fourth member of staff to be named a fellow (he is today a […]

Article  |  Topics: EDA - ESL  |  Tags: ,   |  Organizations:
June 1, 2008

Accentuate the practical

When engineers discuss the status and value of the Design Automation Conference (DAC), one topic tends to recur. Fairly or unfairly, the claim is that there has long been an inherent tension between DAC the technical conference and DAC the exhibition. In short, the technical conference has been seen as biased toward tool developers; the […]

Article  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:

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