Zeroing in on the problems of fast board-level interconnect

By Chris Edwards |  No Comments  |  Posted: June 10, 2014
Topics/Categories: PCB - Design Integrity, EDA - IC Implementation  |  Tags: , , , , , ,  | Organizations: , , , ,

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.

If a board-level multi-gigabit per second channel is generating more noise and jitter than usable data, there is a good chance that the power delivery network is going to play a hand. That was one of the conclusions from a panel organized by Cadence Design Systems at the 51st Design Automation Conference (DAC) in San Francisco.

But the combination of speed, packages and board materials mean power is not going to be the only culprit – designers need to look at all the variables to be sure. Pressure to move inter-package serial speeds up to 56Gbit/s, and in environments where these channels are likely to be bundled into buses, means that the materials involved can have as dramatic an effect on performance as the I/O cells.

Jenny Jiang, principal engineer for signal and power integrity at Altera, said: “The challenge is basically that we have to deal with three things at the same time: signal bandwidth, channel density and the tradeoff of product performance to cost. We don’t want to overdesign our products.

“Packages and boards are no longer conductors, they act like transmission lines with propagation properties that contribute to distortion. When we connect I/O through the package, it’s a totally different story. And when we cascade to the board, it’s a different story again.”

High-speed, board-level I/O calls for accurate measurements to help drive simulations

Image High-speed, board-level I/O calls for accurate measurements to help drive simulations

Dan Weed, director of design solutions at GlobalFoundries, said: “What worked today may not work tomorrow. We are seeing speeds in excess of 28Gbit/s and we are now having routine discussions about the need for 56Gbit/s. In this environment, codesign early and codesign often and partnering early are the keys to success.”

Intel senior staff engineer Xiaoning Qi added: “I’m quite passionate about codesign. We need to look at the platform and how it impacts silicon. The second challenging thing is signal integrity and power integrity codesign. People claim to do codesign but for the real impact of signal integrity and power integrity, we need to dive in deeper to look at things.”

Full codesign presents problems, panelists said, because the chip may be used in different environments that present quite different conditions. “We also have to consider crosstalk with very high channel densities. We can’t really predict what our customers may do at the PCB level,” said Jiang.

Codesign challenges

Even system houses have the issue not being able to tune the chip for a specific combination of package and board environment, said Brad Brim, senior staff product engineer at Cadence. A given SoC may be reused in many different ways inside a product to maximize the ROI for its design.

“You have to be able to account for differences in the fabric. The question is whether I have to create a composite analysis or just be aware of the possible differences. You may not have to do a detailed extraction. And it’s not feasible to go from quantum mechanics to an 18-board system,” Brim said.

When things go wrong, said Weed, it’s important to look for the “signal killers. Those are the areas you try to focus on. It’s where we spend a lot of our time”.

Qi added that the overlap between signal integrity and power integrity is one key focus area. “I would encourage signal-integrity and power integrity [engineers] to expand their domain knowledge from one to the other and expand into the silicon side as well. Look at how the silicon implements the interface. That will help you avoid the root cause of failures.”

Rework specifications

Jiang said a way of heading off problems would be to look again at the system specifications for high-speed I/O. “If we can break down the system specifications into silicon, package and board specs so that when we design these three pieces we can guarantee performance or at least minimize the problems. We need to properly understand the industry specifications. And we need to identify killer factors that reduce system performance.”

In terms of the tools infrastructure, Jiang said there is a need for good metrology to better correlate simulations with hardware measurements. “And we need very sophisticated 3D full-wave extraction tools.”

Weed claimed the issue of I/O modeling is going to move inside the package. “The move to 3DIC and TSVs [through-silicon vias] creates a small system in itself. The parasitics and dynamics in that will start affecting things on the board itself. Customers with large memory requirements need TSVs and what we see with packages today will gravitate to the stacked packages. We are doing that with Spice right now as well as working with Cadence to ensure we have extraction at the TSV and ensure we can move that into the tools.

“We don’t want to do everything at the BSIM level but sometimes it looks like it,” Weed added.

Power-delivery issues

Qi said: “At the end of the day, the tools are just mathematical models. We can’t capture everything in the whole system. We have to find the right critical problem to solve, say jitter.”

The on-chip power-delivery network is often a culprit for jitter. “Noise there couples through into additional jitter,” Brim said.

“A lot of people just look at the I/O’s impact and buffering noise. But is this the most important factor? Signal and power integrity coupling matters. This is much more influential than the I/O buffers,” Qi claimed. “If you see clock jitter, I would suggest go look at the power supply.”

Brim said: “You can wrap a Faraday cage around signaling lines using metallization. But you can’t always separate the power-delivery network. Lots of companies use a global ground and that can cause problems. Power integrity is going to be that globalization of noise effects that you don’t want. And you have got to be able to analyze that impact.”

Brim added that it important not to focus too much on the power network, however: “Historically, signal integrity was everyone’s key focus. What I’ve noticed over time is that there has been a lot of ramp-up in power integrity considerations. Sometimes it’s an overreaction. But I hope it won’t swing too far back the other way. The two [signal integrity and power integrity] are required to do your verification.”

As the pressure mounts to double per-channel datarates again to 112Gbit/s, Upen Reddy, senior technical leader in the enterprise networking group at Cisco Systems, said conventional approaches could run out of steam and that it may be time to move to more exotic signaling schemes, such as the quadrature-amplitude modulation (QAM) commonly used in RF engineering as part of the recipe to provide additional bandwidth in a noisy, unpredictable environment. “I want to see codesign start to include them, and even optical design,” said Reddy.

“If you look at this business, statistically everything should not work but it does,” said Weed. “We can’t take our eye off the ball because it’s going to get blindingly fast. When we get to finFET, hold on.”

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