System Verilog

February 26, 2020

DVCon US 2020 preview: Verific

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.

Article | Topics: Blog Topics, Conferences, Blog - EDA, - Tool development, Verification | Tags: C, INVIO, parser, Python, System Verilog, VHDL | Organizations: DVCon, Verific

November 12, 2015

DVCon Europe: UVM-SystemC backers ready first draft

But the bridge standard's European backers still need greater support from the big EDA vendors.

Article | Topics: Commentary, Conferences, Blog - EDA, Embedded, - ESL/SystemC, Verification | Tags: System Verilog, UVM, virtual prototyping | Organizations: Cadence Design Systems, Continental, Doulos, DVCon Europe, Fraunhofer Institute, Infineon Technologies, Magillem Design Services, NXP Semiconductors

February 3, 2015

Speeding up simulation using native System Verilog transactors

Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.

Article | Topics: Blog - EDA, - Verification | Tags: emulation, partitioning, System Verilog, transactors, UVM | Organizations: Synopsys