Mentor adds rapid RFQ to Capital suite
Wire harness margins are tight yet quotes still need to be turned on a dime. Integrating that process into existing tools aims to help.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Gartner: Multi-patterning here to stay, EUV lithography still 50:50
Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group
DAC 2013 Preview VIII: Low-power design
Sessions at the DAC 2013 conference in Austin, Texas focus on low-power design and engineering low-energy systems from the system level down to physical.
DAC 2013 Preview VII: Verification and simulation
DAC 2013’s technical program has four sessions on innovation for verification. Some of the hot topics being covered include 3DIC and analog.
Automotive benchmark puts focus on power consumption
Vehicle-maker Volkswagen is putting its weight behind a set of microcontroller benchmarks that focus on energy consumption rather than performance.
Aldec automates safety-critical traceability
Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.
DAC 2013: The Gary Smith EDA ‘what to see’ list is live
Whether your going to DAC 2013 or not, the EDA analyst’s round-up is an invaluable guide to design trends and the tool vendors most actively addressing them.
Cadence tackles timing signoff with Tempus
Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.
TVS expands VIP library
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
SureCore picks up grant for low-power, nanometer SRAM IP
Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.