Altera finds a way to cheaper floating point in FPGAs
Altera has revealed that the DSP blocks in the Arria 10 FPGAs contain the logic needed to make them work as IEEE754-compliant floating-point units.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Cadence to expand formal portfolio with Jasper buy
Cadence Design Systems has reached an agreement with Jasper Design Automation to buy the formal-verification specialist for $170m in cash.
FinFET variability issues challenge advantages of new process
Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.
Verification perspectives: the growth of emulation
The first in a series of articles on how various vendors are addressing the flow’s most challenging task looks at Mentor’s strategy for emulation.
Common Platform foundry alliance to be wound down
But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.
Mentor builds simulation-emulation bridge to ‘Verification 3.0’
Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
ARM moves to open-source compiler
ARM has decided to shift from using its in-house compiler technology to the open-source combination of Clang and LLVM.
Latest ITRS underlines slowdown in interconnect and IC scaling
The 2013 edition of the International Technology Roadmap for Semiconductors has been published. The latest set of tables underlines the slowdown in some aspects of scaling, particularly when it comes to metal interconnect.
DAC 2014 offers free exhibit entry for three days
The 51st Design Automation Conference, to be held in San Francisco in early June, is offering free exhibit floor entry for the full three days.
Silicon suppliers home in on energy-harvesting sensor nodes
Power converters are arriving on the market with the aim of simplifying the job of building energy-harvesting systems for wireless sensor nodes and the Internet of Things.